Resource Assignment in a Compiler for Transport Triggered Architectures

Compiler Strategies for Transport Triggered Architectures

Evaluating transport triggered architectures for scalar applications

In transport triggered architectures (TTAs) the programming and operational model is mirrored when compared with regular RISC and VLIW architectures; instead of programming operations which cause data transports as side eeects, in TTAs the transports are programmed, where a transport may trigger an operation if necessary. Transports are therefore visible at the architecture level, and are compl...

Energy Efficient Code Generation for Processors with Exposed Datapath

In a modern processor architecture the register file (RF) consumes considerable amount of power. Therefore it is important to reduce the RF accesses when designing an energy efficient architecture. It is well-known that with datapath exposed to software, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic. In this paper, we analyze the potential of using MOVE-Pr...

On Efficiency of Transport Triggered Architectures in DSP Applications

The trend in programmable architectures for digital signal processing (DSP) is to move towards high-level language programming, which sets high requirements for compilers to efficiently exploit the instruction level parallelism in modern processors. In this paper, efficiency of transport triggered architectures (TTA) in DSP applications is discussed. The efficiency of a high-level compiler on a...

Register Bank Assignment for Spatially Partitioned Processors

Demand for instruction level parallelism calls for increasing register bandwidth without increasing the number of register ports. Emerging architectures address this need by partitioning registers into multiple distributed banks, which offers a technology scalable substrate but a challenging compilation target. This paper introduces a register allocator for spatially partitioned architectures. ...